A regulator is a circuit that supplies power from a source at a controlled or regulated level of voltage and/or current. Linear and switching regulators are known, for providing regulated direct current (DC) power for modern electronic devices. A switching regulator uses an energy storage circuit, typically formed by a capacitance, an inductance (e.g. inductor or transformer) or a combination thereof, together with one or more switches to effectively transfer electrical energy from the source to a regulated output. Advantages of switching regulators are well known. One particular advantage of the switching approach is that it is a fairly simple matter to rearrange the energy storage circuit and switches to convert voltage up (boost), convert voltage down (buck) or provide a voltage inversion.
As the DC/DC converter/regulator circuit operates to switch between circuit states, power is transferred in discrete units or packets. Switched power transfer, however, creates noise or ripple in the flow of input current from the power source, which tends to generate on-chip voltage spikes and EMI. As switching rates of DC/DC switching converters are increasing (>IMHz), on-chip transients and radiated EMI due to switch node transition are becoming an issue. Due to higher operating frequencies, it is desirable to minimize the transition time required when switching to minimize power losses and blanking time for switch settling. Blanking time is the time between turn-off of one switch and the time of turn-on of the other switch, typically, to avoid shoot-through. Unfortunately fast slewing of the switch node to minimize the transition time results in high on-chip supply transients and high external radiated EMI. It may be helpful to consider an example.
FIG. 1a is a circuit diagram showing the switch circuit for a DC-DC converter (with energy storage elements omitted, for convenience). Although connection to the energy storage elements will vary depending on the desired application, buck, boost or inverter, the principal elements and arrangement of the switching circuit will be substantially similar.
The circuit diagram shows a buck converter switch configuration with very fast turn on and turn off times. A p-type metal oxide semiconductor (PMOS) type field effect transistor (FET) P1 selectively connects input voltage VIN through a small resistance (typically an on-chip metal resistance) to a switch node SW. An n-type metal oxide semiconductor (NMOS) FET transistor N1 selectively connects switch node SW to ground, through small resistance (typically metal-on-chip resistance). The switching transistors P1 and N1 are relatively strong transistors, for efficiency, in that the characteristic impedance from drain to source, when each transistor is on, is very low. Because the impedance is low, the voltage drop across the on transistor is low for a given current through the transistor, and the transistor consumes relatively little operating power. Each switch has to hold the switch node SW at the desired state (connected to VIN through P1, or connected to ground through N1), but it is desirable for the respective transistor to hold the state while consuming relatively little power. Hence, the transistors P1 and N1 are much stronger than would normally be needed to hold the switch node SW in the respective state. Often, the characteristic impedance from drain to source is on the order of 1Ω or less, commonly on the order of tens to hundreds of mΩ, to achieve 90% efficiency for the regulator circuit. Impedance is sized to facilitate desired output requirements of the particular converter application.
The current source load (ILOAD) represents the standing current in the inductor L of the buck converter. The inductor L of the buck converter is connected from the switch node SW to the output voltage (VOUT) node shown. The other elements of the circuit shown in FIG. 1a relate to the logic circuitry to control the timing of the switching on and off of the switching transistors P1 and N1, in response to the high-speed switching signal VCLK.
Because the transistors P1 and N1 are strong transistors, they can transition the switch node SW quickly.
FIG. 1b shows selected switching waveforms for the circuit in FIG. 1a (assuming that VIN=5V and ILOAD=1 A). In FIG. 1b, the upper graph shows the current (I) that flows through resistor RB2, that is, the input current flowing from the source VIN. The upper graph also shows the absolute value of the change (dI/dt) of the current from the input, referred to as ABS(DI(RB2))/dt) (in A/ns) in the drawing. The two spikes in the graph ABS of current change dI/dt, in the example, exceed 4.0 amps/nanosecond (A/ns). These spikes represent the edge rates in the transitions of the current flow I(RB2) in Amps (A), as also shown in the drawing. The first spike corresponds to a transition from high to low in the current trace (I(RB2)) and represents the rate at which the input current I turns off. The second spike in the ABS trace for the change (dI/dt) of the current corresponds to a transition from high to low in the current trace (I(RB2)) and represents the rate at which the input current I turns on. The lower graph in FIG. 1b depicts several of the voltages as they appear at different times in the circuit of FIG. 1a. The time scale of the upper and lower graphs coincide.
Assume that the circuit is in a state in which current I(RB2) is flowing through PMOS transistor P1 (see left portion of FIG. 1b). The waveforms V(P1) and V(N1) of FIG. 1b are the gate voltages of the PMOS (P1) and NMOS (N1) respectively. A PMOS turns on with a negative gate-source voltage. Since the source of P1 is at the input supply, P1 is on (low impedance) when V(P1) is low and off (high impedance) when V(P1) is high. Conversely a NMOS turns on with a positive gate-source voltage. Since the source of N1 is at ground, N1 is on (low impedance) when V(N1) is high and off (high impedance) when V(N1) is low. For the case where transistor P1 is on, and NMOS transistor N1 is off, we see that both V(P1) and V(N1) are both low. The low impedance of P1 drives the switch node voltage V(SW) high.
Now assume that it is time to transition from the state where V(SW) is high to a state in which the switch node voltage V(SW) is low, which means that the NMOS transistor N1 is on and no current is flowing through PMOS transistor P1. The transition must not allow both transistors P1 and N1 to be on at the same time (shoot-through), as this would allow a very large current flow through the low impedance switches and resistances to ground. Hence, the logic of the circuit will turn the PMOS transistor P1 off before turning the NMOS transistor N1 on.
When the SW node transitions low, the input current I(RB2) remains very high as the switch node transitions low and is quickly shut off when the SW node goes low enough to turn on the drain to substrate diode of NMOS (N1). More specifically, the SW node voltage V(SW) does not start slewing down until the drive to the PMOS P1 gate is reduced to the point where PMOS P1 can no longer supply the load current ILOAD (standing inductor current in the case of a buck converter). As the PMOS P1 gate drive is further reduced, the voltage V(SW) on the SW node will start to drop, but parasitic Miller capacitance and SW-to-VIN capacitance on the large PMOS transistor P1 keep the input current I(RB2) high, as the node voltage V(SW) transitions low. However, the input current very abruptly goes to zero as the SW node voltage bottoms out into the NMOS (N1), which is acting as a diode clamp.
The sudden drop in input current produces the spike, shown to the left in the upper graph of the current change. As the waveforms show, the supply pin switching current dI/dt is greater than 5 A/ns. At this rate, 1 nH of bond wire/pin inductance will induce a 5V spike on the input supply of an Integrated Circuit (IC). Additionally, the switch node transitions the full supply range in under 1 ns, which is undesirable from an EMI point of view.
The most common method of controlling the switch node transition is to drive the large switches of a DC/DC converter with weak drivers. The weak drivers slow the turn-on/turn-off time of the large switches, effectively reducing the slew rate of the switching node. However, this can result in undesirably long switch settling times for appreciable reductions in switch node slew rate and on-chip switching transients. Consider the following.
FIG. 2a is a circuit diagram showing a switch circuit for a DC-DC converter (again with the energy storage elements omitted, for convenience) for delivering a 5V output with a 1 A load current. Again, although the connection to the energy storage elements will vary depending on the desired application, buck, boost or inverter, the principal elements and arrangement of the switching circuit will be substantially similar.
The circuit of FIG. 2a is similar to that of FIG. 1a, except that the circuit of FIG. 2a implements the known technique for reducing problematic noise. FIG. 2a shows a buck switch configuration with the gate drive to the large PMOS (P1) and NMOS (N1) switches significantly reduced over that in FIG. 1a. In the example of FIG. 2a, the circuit uses higher impedance (weaker) inverters U5 and U15, to drive the gates of the strong switching transistors P1 and N1. The inverter U5 and U15 that drive the gates of the large PMOS (P1) and NMOS (N1) transistors are smaller, and thus presents a higher drive impedance at the respective gate of P1 or N1, than the comparable elements in the circuit of FIG. 1a. As a result, the higher impedance takes longer to discharge the Miller capacitance (from the source back to the gate) of P1 or N1, and tends to hold the respective transistor on longer in transitions. This tends to slow the slew rate of the switching transistors when transitioning from on to off or from off to on. Reducing the slew rate reduces the spikes in dI/dt that generate undesirable voltage spikes and EMI.
FIG. 2b shows selected switching waveforms for the circuit in FIG. 2a. Limiting the drive to the large PMOS and NMOS switches, as in the circuit of FIG. 2a, reduces the slew rate of the switching node. For example, in the transition of the switch node voltage V(SW) from on to off, the slope of the drop off is not as steep, and when the switch node voltage V(SW) bottoms out into the clamp diode of transistor N1, the current transition will be less abrupt. This effectively reduces the radiated EMI and shrinks the overall dI/dt transients on the supply input. Note that in this topology much of the switching time represents getting to/from the threshold voltage of the PMOS P1 or NMOS N1.
This method of drive control provides reduced supply current spikes, but at the expense of longer drive switch transition times. In the case of FIG. 2b, 2 A/ns dI/dt spikes are induced on the input supply. However, the time it takes the switches to settle out is nearly doubled. A dI/dt of 2 A/ns with 1 nH of bond wire inductance still will induce a 2V spike on the input supply voltage of an IC.
As shown by the example of prior art of FIGS. 2a, 2b, one is fighting a losing battle between total switching time and minimizing supply transients caused by slewing the switching node. Also, as the transition time of the switch node (SW) is not significantly reduced, only a minimal improvement in radiated EMI has been achieved.
The switches of DC/DC converters are generally made very large to reduce their effective impedance, thus reducing switch power loss. Because of this, transition from off to on of the PMOS (P1) and NMOS (N1) for a given inductor current occurs over a small range of the gate voltage swing. Since the actual gate voltage range for switch node transition is a very small portion of the total gate voltage swing, most of the switching time will be wasted transitioning to and from this control point. There are many variants of the prior art discussed above, but all known techniques for mitigating the effects of switching noise are based on reducing the drive to the converter switches (P1, N1) to control the slew rate of the switching node, which is fundamentally flawed for the reasons just presented.
Hence a need still exists for a technique of effectively mitigating the switching noise, that will still provide relatively fast total switching time.